1. Field of the Invention
This invention relates to a semiconductor having protruding contacts comprising, a first semiconductor substrate having at least one interconnect located substantially within the first substrate, and a second semiconductor substrate having at least one protruding contact point that substantially contacts at least one interconnect.
2. Description of the Related Art
Prior to the present invention, as set forth in general terms above and more specifically below, it is known in the semiconductor art, that two semiconductor substrates can be joined together at low temperatures by using well-known plasma-enhanced bonding processes. These low-temperature substrate joining techniques can be used to package MEMS (microelectromechanical systems) or NEMS (nanoelectromachanical systems) devices hermetically as well as 3-D wafer stacking. With respect to these low-temperature substrate joining techniques, the surface of the substrates to be joined need to be flat and very smooth (<20 A rms surface roughness over 2 μm×2 μm). Consequently, the surfaces are usually planarized with chemical mechanical polishing (CMP).
It is well known that the CMP planarization process creates some unique challenges for wafer-to-wafer interconnect applications since it is difficult to planarize the interconnect plug (or contact points) and the surrounding area evenly. The interconnect between two substrates may fail if dishing on the plugs occurs during the CMP process. Also, plasma-enhanced bonding may fail if the plugs surfaces are higher than the surrounding area, which prevents the two substrates from contacting at the atomic level.
It is also known, in the semiconductor art, that compliant intermediate layers (such as BCB (benzocyclobutene)) are often used to adhere two substrates together as well as to form an interconnect at the same time. This approach works fine for many 3-D interconnect applications, but does not work when both 3-D interconnect and hermetic packaging are required since BCB is not hermetic.
It is further known, in the semiconductor art, that Au bump or solder ball techniques can be used to flip-chip bond one substrate to another. However, none of these techniques provide both a good electrical interconnect between the substrates and hermetic packaging at the wafer level as the bumps or balls tend to cause a standoff between the circuits or substrates. The interconnect density is also limited with this approach.
Finally, it is known, in the interconnect art, to bond the interconnect to the pad of the circuit device. Typical techniques involve heat, eutectic bonding, electrical bonding, and/or mechanical bonding. However, many of these techniques do not provide an adequate bond for a variety of reasons.
It is apparent from the above that there exists a need in the semiconductor art for a semiconductor construction technique that works with both 3-D interconnect and hermetic packaging, but which at the same time allows the two substrates to be efficiently bonded so that they contact each other at the atomic level. It is a purpose of this invention to fulfill this and other needs in the art in a manner more apparent to the skilled artisan once given the following disclosure.